pa07 ? PA07A pa07u 1 pa07, PA07A typical application negates optoelectronic instabilities lead network minimizes overshoot sequential position control position is sensed by the differentially connected photo diodes, a method that negates the time and temperature variations of the optical components. off center positions produce an error current which is integrated by the op amp circuit, driving the system back to center position. a momen - tary switch contact forces the system out of lock and then the integrating capacitor holds drive level while both diodes are in a dark state. when the next index point arrives, the lead network of c1 and r1 optimize system response by reducing overshoot. the very low bias current of the pa07 augments performance of the integrator circuit. external connections note: input offset voltage trim optional. r t = 10k max features ? low bias current fet input ? protected output sta ge thermal shutoff ? e xcellent linearity class a/b output ? wide suppl y range 12v to 50v ? hi gh output current 5a p eak applications ? motor, v a lve and actuator control ? ma gnetic deflection circuits up to 4a ? power transducers up to 100khz ? temp erature control up to 180w ? pro grammable p ower supplies up to 90v ? a udio amplifiers up to 60w rms description the pa07 is a high voltage, high output current operational amplifer designed to drive resistive, inductive and capacitive loads. for optimum linearity, especially at low levels, the out - put stage is biased for class a/b operation using a thermistor compensated base-emitter voltage multiplier circuit. a thermal shutoff circuit protects against overheating and minimizes heatsink requirements for abnormal operating conditions. the safe operating area (soa) can be observed for all operating conditions by selection of user programmable current limiting resistors. both amplifers are internally compensated for all gain settings. for continuous operation under load, a heatsink of proper rating is recommended. this hybrid circuit utilizes thick flm (cermet) resistors, ceramic capacitors and semiconductor chips to maximize reliability, minimize size and give top performance. ultrasonically bonded aluminum wires provide reliable interconnections at all operating temperatures. the 8-pin to-3 package is hermetically sealed and electrically isolated. the use of compressible washers and/or improper mounting torque will void the product warranty. please see general operating considerations. equiv alent schem atic cl+ +v +in Cin Cv bal clC out s s top view r cl+ r clC r t r s output r s = ( v s + + Cv s ) r t /1.6 1 2 3 4 5 6 7 8 motor r cl+ r clC c l c f r l r f2 r f1 +32v .68 .68 C32v +v Cv pd1 pd2 light v = 28 emf = 14v r = 14 pa07 w 3 7 5 4 6 2 1 8 q1 q2 q5 q4 q3 q8 q9 c3 q12a q12b q10 q15 q18 d2 d3 d1 c2 c4 q11 q16 q19 c1 q7 q6a q6b q17a q17b 8-pin to-3 p ac ka ge style ce fet input power operational amplifier pa07 ? PA07A p r o d u c t i n n o v a t i o n f r o m copyright ? cirrus logic, inc. 2009 (all rights reserved) http://www.cirrus.com may 2009 apex ? pa07urevp p r o d u c t i n n o v a t i o n f r o m
pa07 ? PA07A 2 pa07u specifications absolute maximum ratings supply voltage, +v s to Cv s 100v output current, within soa 5a power dissipation, internal 1 67w input voltage, differential 50v input voltage, common mode v s temperature, pin solder - 10s 300c temperature, junction 1 200c temperature range, storage C65 to +150c operating temperature range, case C55 to +125c pa07 PA07A parameter test conditions 2 min typ max min typ max units input offset voltage, initial t c = 25c .5 2 .25 .5 mv offset voltage, vs. temperature full temperature range 10 30 5 10 v/c offset voltage, vs. supply t c = 25c 8 * v/v offset voltage, vs. power full temperature range 20 10 v/w bias current, initial 3 t c = 25c 5 50 3 10 pa bias current,vs. supply t c = 25c .01 * pa/v offset current, initial 3 t c = 25c 2.5 50 1.5 10 pa input impedance, dc t c = 25c 10 11 * input capacitance t c = 25c 4 * pf common mode voltage range 4 full temperature range v s C10 * v common mode rejection, dc full temperature range, v cm = 20v 120 * db gain open loop gain at 15hz t c = 25c, r l = 15 89 95 * * db gain bandwidth product @ 1mhz t c = 25c, r l = 15 1.3 * mhz power bandwidth t c = 25c, r l = 15 18 * khz phase margin full temperature range, r l = 15 70 * output voltage swing 4 full temp. range, i o = 5a v s C5 * v voltage swing 4 full temp. range, i o = 2a v s C5 * v voltage swing 4 full temp. range, i o = 90ma v s C5 * v current, peak t c = 25c 5 * a settling time to .1% t c = 25c, 2v step 1.5 * s slew rate t c = 25c 5 * v/s capacitive load, unity gain full temperature range 1 * nf capacitive load, gain>4 full temperature range soa * power supply voltage full temperature range 12 35 50 * * * v current, quiescent t c = 25c 18 30 * * ma thermal resistance, ac, junction to case 5 f>60hz 1.9 2.1 * * c/w resistance, dc, junction to case f<60hz 2.4 2.6 * * c/w resistance, junction to air 30 * c/w temperature range, case meets full range specifcations C25 25 +85 * * * c notes: * the specifcation of PA07A is identical to the specifcation for pa07 in applicable column to the left. 1. long term operation at the maximum junction temperature will result in reduced product life. derate internal power dissipation to achieve high mttf. 2. the power supply voltage for all specifcations is the typ rating unless otherwise noted as a test condition. 3. doubles for every 10c of temperature increase. 4. +v s and Cv s denote the positive and negative supply rail respectively. total v s is measured from +v s to Cv s . 5. rating applies if the output current alternates between both output transistors at a rate faster than 60hz. the internal substrate contains beryllia (beo). do not break the seal. if accidentally broken, do not crush, machine, or subject to temperatures in excess of 850c to avoid generating toxic fumes. caution p r o d u c t i n n o v a t i o n f r o m
pa07 ? PA07A pa07u 3 40 100 total supply voltage, v s (v) .4 .6 1.6 quiescent current normalized quiescent current, i q (x) .8 1.4 50 60 70 80 90 1.2 1.0 t c = C25c t c = 25c t c = 85c t c = 125c 0 2 3 6 output current, i o (a) 0 2 6 output voltage swing voltage drop from supply, v sat (v) 3 5 1 5 1 4 4 t c = 25c t c = 85c t c = C25c C15 25 105 .06 1 64 256 bias current 4 .25 5 45 65 85 16 temperature, t c (c) normalized bias current, i b (x) 0 20 40 60 80 100 120 0 10 30 50 power derating internal power dissipation, p (w) 20 70 140 40 60 t = t c t = t a temperature, t c (c) 1 100 10m frequency, f (hz) C20 0 60 120 small signal response open loop gain, a ol (db) 20 40 80 100 10 1k 10k .1m 1m 1 100 .1m 10m C180 C150 C60 0 phase response C90 C30 1k 10 10k 1m frequency, f (hz) phase, () C120 C210 C50 C25 50 100 case temperature, t c (c) 0 3.0 current limit current limit, i lim (a) 2.5 0 25 75 1.0 1.5 .5 2.0 r cl = 0.6 r cl = 0.3 1 10k frequency, f (hz) 0 common mode rejection common mode rejection, cmr (db) 40 80 120 .1m 10 100 1k 1m 20 60 100 0 time, t (s) pulse response output voltage, v o (v p-p ) C8 2 4 6 8 10 12 C6 C4 C2 0 2 4 6 8 v in = 5v, t r = 100ns 10k 20k 50k .1m frequency, f (hz) 4.6 output voltage, v o (v p-p ) power response 30k 70k 6.8 10 15 22 32 46 68 100 |+v s | + |-v s | = 100v |+v s | + |-v s | = 70v 10 100 10k .1m frequency, f (hz) input noise voltage, v n (nv/hz) input noise 1k 2 10 20 4 6 100 1k 3k .1m frequency, f (hz) .3 3 harmonic distortion distortion, thd (%) .01 .1 1 300 10k 30k .03 p o = 50w, v s = 25v, r l = 4 p o = 50mw, r l = 8 g =10 10 p o = 60w, v s = 36v, r l = 8 p r o d u c t i n n o v a t i o n f r o m
pa07 ? PA07A 4 pa07u general please read application note 1 "general operating con - siderations" which covers stability, supplies, heat sinking, mounting, current limit, soa interpretation, and specifcation interpretation. visit www.cirrus.com for design tools that help automate tasks such as calculations for stability, internal power dissipation, current limit; heat sink selection; apex precision powers complete application notes library; technical seminar workbook; and evaluation kits. sa fe op erating area ( soa) the output stage of most power amplifers has three distinct limitations: 1. the current handling capability of the wire bonds. 2. the second breakdown effect which occurs whenever the simultaneous collector current and collector-emitter voltage exceed specifed limits. 3. the junction temperature of the output transistors. sa fe op erating area curves the soa curves combine the effect of these limits. for a given application, the direction and magnitude of the output current should be calculated or measured and checked against the soa curves. this is simple for resistive loads but more complex for reactive and emf generating loads. however, the following guidelines may save extensive analytical efforts. 1. for dc outputs, especially those resulting from fault condi - tions, check worst case stress levels against the new soa graph. for sine wave outputs, use power design 1 to plot a load line. make sure the load line does not cross the 0.5ms limit and that excursions beyond any other second breakdown line do not exceed the time label, and have a duty cycle of no more than 10%. for other waveform outputs, manual load line plotting is recommended. applications note 22, soa and load lines, will be helpful. a spice type analysis can be very useful in that a hardware setup often calls for instruments or amplifers with wide common mode rejection ranges. tc = 125c thermal steady state second breakdown t = 1ms t = 5ms t = 0.5ms .2 .3 .4 .6 .8 1.0 1.5 2.0 3.0 4.0 5.0 10 15 20 25 30 35 40 50 60 70 80 100 tc = 85c supply to output differential voltage v s C v o (v) output current from +v s or C v s (a) 2. the amplifer can handle any reactive or emf generating load and short circuits to the supply rail or common if the current limits are set as follows at t c = 85c: short to v s short to v s c, l, or emf load common 50v .21a .61a 40v .3a .87a 30v .46a 1.4a 20v .87a 2.5a 15v 1.4a 4.0a these simplifed limits may be exceeded with further analysis using the operating conditions for a specifc application. 3. the output stage is protected against transient fyback. however, for protection against sustained, high energy fyback, external fast-recovery diodes should be used. thermal sh utdown p rotection the thermal protection circuit shuts off the amplifer when the substrate temperature exceeds approximately 150c. this allows heatsink selection to be based on normal operating conditions while protecting the amplifer against excessive junction temperature during temporary fault conditions. thermal protection is a fairly slow-acting circuit and therefore does not protect the amplifer against transient soa violations (areas outside of the t c = 25c boundary). it is designed to protect against short-term fault conditions that result in high power dissipation within the amplifer. if the conditions that cause thermal shutdown are not removed, the amplifer will oscillate in and out of shutdown. this will result in high peak power stresses, will destroy signal integrity and reduce the reliability of the device. current limit proper operation requires the use of two current limit resis - tors, connected as shown in the external connections diagram. the minimum value for r cl is .12, however, for optimum reliability it should be set as high as possible. refer to the general operating considerations section of the handbook for current limit adjust details. 1 note 1. power design is a self-extracting excel spreadsheet available free from www.cirrus.com p r o d u c t i n n o v a t i o n f r o m
pa07 ? PA07A pa07u 5 cont acting cirrus logic support for all apex precision power product questions and inquiries, call toll free 800-546-2739 in north america. for inquiries via email, please contact apex.support@cirrus.com. international customers can also request support by contacting their local cirrus logic sales representative. to fnd the one nearest to you, go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnifcation, and limitation of liability. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives con - sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe prop - erty or environmental damage (critical applications). cirrus products are not designed, authorized or warranted to be suitable for use in products surgically implanted into the body, automotive safety or security devices, life support prod - ucts or other critical applications. inclusion of cirrus products in such applications is understood to be fully at the cus - tomers risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customers customer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including attorneys fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs, apex precision power, apex and the apex precision power logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. p r o d u c t i n n o v a t i o n f r o m
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